ASSIST_DEBUG_CORE_0_INTR_CLR_REG
CORE_0_AREA_DRAM0_0_RD_CLR | reg_core_0_area_dram0_0_rd_clr |
CORE_0_AREA_DRAM0_0_WR_CLR | reg_core_0_area_dram0_0_wr_clr |
CORE_0_AREA_DRAM0_1_RD_CLR | reg_core_0_area_dram0_1_rd_clr |
CORE_0_AREA_DRAM0_1_WR_CLR | reg_core_0_area_dram0_1_wr_clr |
CORE_0_AREA_PIF_0_RD_CLR | reg_core_0_area_pif_0_rd_clr |
CORE_0_AREA_PIF_0_WR_CLR | reg_core_0_area_pif_0_wr_clr |
CORE_0_AREA_PIF_1_RD_CLR | reg_core_0_area_pif_1_rd_clr |
CORE_0_AREA_PIF_1_WR_CLR | reg_core_0_area_pif_1_wr_clr |
CORE_0_SP_SPILL_MIN_CLR | reg_core_0_sp_spill_min_clr |
CORE_0_SP_SPILL_MAX_CLR | reg_core_0_sp_spill_max_clr |
CORE_0_IRAM0_EXCEPTION_MONITOR_CLR | reg_core_0_iram0_exception_monitor_clr |
CORE_0_DRAM0_EXCEPTION_MONITOR_CLR | reg_core_0_dram0_exception_monitor_clr |